L1 Cache Decomposition for Energy Efficient Processors

The L1 data cache is a time-critical module and, at the same time, a major source of energy consumption. To reduce its energy-delay product, we apply two principles of low power design: specialize part of the cache structure and break down the cache into smaller caches. To this end, we propose a L1 cache that combines new designs of a stack cache and a PSA cache. Individually, our stack and PSA cache designs have a lower energy-delay product than previously proposed designs. In addition, their combined operation is very effective. Relative to a conventional 2-way 32KB data cache, our design containing a 4-way 32KB PSA cache and a 512B stack cache reduces the energy-delay product of several applications by an average of 44%.